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iMX8M enable two QSPI

Question asked by charles huang on May 27, 2019
Latest reply on May 27, 2019 by igorpadykov

Hi,

 

I want to know how to enable two qspi

My setting as below

&qspi {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_qspi>;
        status = "okay";
        flash0: n25q256a@0 {
                reg = <0>;
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "micron,n25q256a";
                spi-max-frequency = <29000000>;
                spi-nor,ddr-quad-read-dummy = <6>;
        };
        flash1: n25q256a@1 {
                reg = <1>;
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "micron,n25q256a";
                spi-max-frequency = <29000000>;
                spi-nor,ddr-quad-read-dummy = <6>;
        };
};
                pinctrl_qspi: qspigrp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x82
                                MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B    0x82
                                MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x82
                                MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x82
                                MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x82
                                MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x82
                                MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK       0x82
                                MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B    0x82
                                MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0   0x82
                                MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1   0x82
                                MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2   0x82
                                MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3   0x82
                        >;
                };

but it's not working, and it will hang system and kernel panic message
The attached is the dmesg

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