NXP has altered the CMSIS-Sources (from here https://github.com/ARM-software/CMSIS_5) and added an extra “register”-qualifier (see below-left the NXP Version – below-right, the one from the CMSIS-Library):
With the original code (https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS/Core/Include/core_cm7.h) the execution enters an endless loop when trying to disable the Data-Cache (--> calling the SCB_DisableDCache () function from the CMSIS Library)
This problem is only valid when using memory which is cached. When using the TCM only everything runs fine. Same with enabling the optimization – with optimization everything is fine.
I cross-checked with STM32F7 and Kinetis KV58. They work fine with the original code. Why is this change necessary? Is an errata for the cache handling for the iMXRT family available?
Thanks and best regards