I use linflexd with Tx & Rx (with timeout) DMA enabled. Everything works fine until I get into STOP mode. I want to be wokenup from linflex1 and receive all bytes that appear on the rx line. Just before entering STOP mode I disable Rx timeout interrups and set DMA descriptor to receive 32 bytes which always arrive. My idea is that when the bytes arrive during the sleep and are stored into RAM by DMA engine, DMA Rx interrupt is generated in which I reenable Rx timeous, and setup Rx DMA descriptor to receive more bytes and start working as normal.
Problem is, that when I receive Rx DMA interrupt I always see missing the fifth byte. All the first four bytes and the rest after the fifth byte are received correctly. It seems to me that DMA is started only after the FIFO is full during the arrival of the fifth byte and thanks to it it is lost. But no overflow flag is set.
I also performed another test. Decreased speed to 9600 and set DMA desriptor to receive 1 byte. After the bytes start arriving during sleep I get dma rx interrupt indicating one byte transfer but in the interrupt I read out the rx FIFO (reading BDRM.B.DATA4 while UARTSR.DRFRFE is 0 indicating nonempty rx FIFO) and I found out that the FIFO contains 3 more bytes. If DMA started immediately after the first byte is received into FIFO, I don't think 3 more bytes at speed 9600 would manege it into the FIFO.
Could you please give me a hint why the 5th byte is always lost? Am I missing anything? Or how to wakeup form STOP mode from linflex and not loose any byte?
RUN and LP configuration for LINFLEX is 'always run'. That is run both in all run (RUN0,.., DRUN) modes and run in all low power modes (HALT, STOP,..).
Thank you very much for any help