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Configuration of NMI line from SBC to MPC5777C for INTB?

Question asked by Vaibhav Sharma on May 21, 2019
Latest reply on May 23, 2019 by David Tosenovjan



I am using FS6513CAE with MPC5777C in the project. The pin INTB is connected to the NMI pin of MCU. The INTB is generating an interrupt when IO_0 undergoes state change(Verified on oscilloscope). The SIU_EISR register doesn't show the NMI0 bit getting changed(Stays 0- No NMI event has occurred on the NMI input of Core0). So, MCU is not acknowledging the interrupt & ISR is not getting hit obviously. IVOR1 handler is present in the project.


Current configurations done on MCU for the NMI pin-

1. GPIO pad 213 configured as NMI alternate functionality, pin direction is input only.

2. SIU.DIRER.B.NMISEL8= 0;   /*Routing interrupt as NMI (IVOR1 handler) to Core0*/

3.  SIU.IFEER.B.IFEE_NMI8= 1;    /*Enabling the falling edge event for Core0*/



Have I missed any part of the configuration; because of which, I am not getting interrupt acknowledged in the SIU_EISR register???


Thanks in advance.