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IMX7 RGMii KSZ8795 interface issues and U-Boot testing.

Question asked by DAVID SABALESKY on May 20, 2019
Latest reply on May 21, 2019 by Yuri Muhin

I am working with Compulab's IMX7 SOM and KSZ8795CLX Ethernet switch, 4 PHY and 1 GMAC.

I now have the correct TXn - TXn, RXn-RXn signal pairings - original RXn-TXn pair was incorrect.

I believe I also need a 125MHz signal as a ref clock pin on the SOM, ENET_REF_CLK.

Can I use the RXCLK from the PHY as the source for this signal?

I am checking with Compulab on what SOM pin they use in their initial setup for this reference clock for testing.

I understand clock delays may need to be added either by PCB trace or internal registers to accommodate Gig speed.

Does the IMX7 have internal registers that can set these delays?

We are using only Mii (MDC/MDIO) interface to the KSZ8795 and  there is no access to clock skew registers in the PHY.

Trace delay is simple and adds approx 9.8in length at 1.8ns. This is a relatively long trace where my routing is limited.

I can use a clock buffer as well to add delay and not worry about increase in trace length.

If anyone has a schematic using IMX7 and KSX8795, please forward link.


I am testing right now the RGMii interface using U-Boot MII.

I can see the PHY registers using Mii, however the RGMii port cannot ping from U-Boot, even at 10/100MBs speeds.

What additional setups if any needed to be made to fully test from U-Boot?

From what I have read you can ping and test functionality of RGMii from U-Boot.


Any suggestions?

Your help is greatly appreciated.