As said in the heading, I try to find out where half the systemclock go in the HCS08QE128.
The ICS is set as reset default in FEI mode, BDIV=01 or /2, RDIV=0 or /1. DRS=00, DMX32=0 -> FLL factor =512. Frequency is 31250Hz
From this I get the frequency to be (31250*512)/1/2=8MHZ, but the correct answer is 4MHz.
In the previous version of the ICS the DCO output is apparently divided by 2. But this is not specified in the version 3 of the ICS. Is this the reason for the half frequency?
I have studied the QE128 reference manual and the 'HCS08 Unleashed Designer's guide' but I can't figure any logical reason for the difference.
Could anyone put me in the correct direction for some further documentation?
Message Edited by Tbspd_TOK on 2009-02-04 07:07 AM