I'm using 2 cores (both z4) of the MPC, where each core uses some peripherals. However all interrupt vectors are configured to be executed on core1. When I initialize for example the SPI5 peripheral on core1, the PSR342 shows that the interrupt is sent to both cores. During initialization the default (core0 target) bit is not cleared, only the core1 target is added.
What is the recommended way to prevent this? I know I can remove the core0 target manually, but maybe there is a nicer solution? I'm using SDK RTM 2.0.0