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DRAM_SDCLK0 or DRAM_SDCLK1 need to use if we are using two DDR3L

Question asked by Sagar Kumar on May 16, 2019
Latest reply on May 16, 2019 by igorpadykov



We are using two DDR3L in our design using i.MX6 Quad. Let me know we have to use DRAM_SDCLK_0 or DRAM_SDCLK_1 of i.MX6Q to interface two DDR3L Clocks


In Sabre brd, They are using DRAM_SDCLK_0  for Data32 to Data63 and DRAM_SDCLK_1 for Data0 to Data31, Please let me know why they follow this convention and what i have to follow since i am using two DDR3L only (DATA0-31)