I have a question about the LPC546 MCU.
The datasheet says the max ADC clock frequency is 80MHz.
"In the synchronous operating mode, this ADC clock is derived from the system clock.
In this mode, a programmable divider is included to scale the system clock to the
maximum ADC clock rate of 80 MHz."
1) Can the input to the ADC CLOCK DIVIDER be 180MHz since my pll_clk is? Or does the 80MHz limit apply to both before and after that divider block?