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Memory Write or Read 64 bytes access Issue.

Question asked by kim pilyeon on May 15, 2019
Latest reply on May 17, 2019 by kim pilyeon

Hi. 

I use to T2080 CPU. 

development environment is 32 bit, UP. 

 

CS1 is setting VME bus system. 

 

write access function is below. 

*(unsigned short *)(vmeVt + DOM01A +0x8) = 0x0101;

As above function, I need to only 2-bytes access.

but, CPU is access read 64 bytes and write 64 bytes. 

because cache line size = 64 bytes?

 

IFC setting value is ..

WRITEADR(r6, r7, T4_IFC_CSPR1_EXT, 0x00000000)
WRITEADR(r6, r7, T4_IFC_FTIM0_CS1, 0xe00e000e) 
WRITEADR(r6, r7, T4_IFC_FTIM1_CS1, 0x0E001F00)
WRITEADR(r6, r7, T4_IFC_FTIM2_CS1, 0x0E00001F) 
WRITEADR(r6, r7, T4_IFC_FTIM3_CS1, 0x00000000) 
WRITEADR(r6, r7, T4_IFC_CSPR1, (VMEBUS_ADRS | 0x0105)) 
WRITEADR(r6, r7, T4_IFC_AMASK1, ~(VMEBUS_SIZE - 1))
WRITEADR(r6, r7, T4_IFC_CSOR1, 0x400c000c) 

 

TLB setting value is below.

addis r4, 0, 0x1009   /* TLBSEL = TLB1(CAM) , ESEL = 0 */
addis r5, 0, HI(_MMU_TLB_VALID | _MMU_TLB_IPROT)
ori r5, r5, _MMU_TLB_SZ_16M /* TS = 0, TSIZE = 16 MByte page size*/
addis r6, 0, HI(VMEBUS_ADRS) /* EPN */
ori r6, r6, _MMU_TLB_ATTR_G                       <=== write back setting
addis r7, 0, HI(VMEBUS_ADRS) /* RPN */
ori r7, r7, 0x0015 /* Supervisor XWR*/
li r8, 0x0

 

I want to know 2-bytes access method. about read and write access. 

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