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MPC551x software interrupts, blrl problem

Question asked by Carl Leskinen on Feb 3, 2009
Latest reply on Jul 11, 2011 by Luo Xianyin
Hi,

I am implementing a software external interrupt on my 551x system, using PIT timer 1 (vector 149). When reading the MPC5510 reference manual, the application note AN2865 and looking at RAppID generated code, they all suggest the same procedure for getting execution to my ISR, which I do:

at init:
1) INTC.MCR.R = 0x0 (SW vect, 4 byte)
2) load INTC.IACKR_PRC0.R = (vuint32_t)&IntcIsrVectorTable_z1; (located at 0x00002000)
3) let IntcIsrVectorTable_z1[149] contain address to PIT ISR: IntcIsrVectorTable_z1[149] = (uint32_t)&pit_isr, which in my case is 0x00003b80
4) set PIT and processor priorities properly (PIT prio 5, core z1 prio 4)

then in my "main" interrupt table, containing all IVOR0-15:

1) at IVOR 4 (in my case 0x00001040) branch to a prolog saving GPR + CR, LR etc in a 0x50 (80 byte) stack frame. Also read INTC_IACKR_PRC0 and save content into LR
2) execute 'blrl' which will branch to LR (containing 0x00002254 - correct), saving return address. It should also move execution to the address specified at this vector 149 but here is where my problems start...

PROBLEM:
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When the processor gets to this point (PC at 0x00002254), it tries to execute the contents of this address which is 0x00003b80. This corresponds to some undefined OPCODE which eventually gives me a IVOR 6 PROGRAM EXCEPTION....

However, if I manually write the OPCODE for branching from vector[149] to &pit_isr, which in my case is 0x48001928 I get a correct behaviour and everything works perfectly...
this does however feel like the much too complicated way of doing this and since all litterature I have found tell me to only put the address of "where I am going" instead of the asm-instruction of how to go there, I feel like I am missing something...

Very grateful for your assistance

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