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When ECSPI uses DMA, SCK will have a low level after every 16 pulses.

Question asked by 永磊 李 on May 14, 2019
Latest reply on May 14, 2019 by 永磊 李

When using IMX6ul ECSPI by DMA, SCK will have a low level after every 16 pulses.Yellow is the SCK line,Linux kernel is 4.1.15.

There is such a description in the data sheet:

20.4.4.1.2 Master Mode with Wait States

     Wait states can be inserted between SPI bursts. This provides a way for software to slow down the SPI burst to meet the timing requirements of a slower SPI device.
    The following figure shows wait states inserted between SPI bursts.

 

In this case, the number of wait states is controlled by ECSPI_PERIODREG[SAMPLE PERIOD] and the wait states' clock source is selected by ECSPI_PERIODREG[CSRC]

20.4.4.1.3 Master Mode with SS_CTL[3:0] Control
      The SPI SS Control (SS_CTL[3:0]) controls whether the current operation is single burst or multiple bursts.

When the SPI SS Wave Form Select (SS_CTL[3:0]) is set, the current operation is multiple bursts transfer. When the SPI SS Wave Form Select (SS_CTL[3:0]) bit is cleared, the current operation is single burst transfer. A SPI burst can contains multiple words as defined in the BURST LENGTH field of the ECSPI_CONREG register.

In Figure 20-8, two 8-bit bursts in the TXFIFO have been combined and transmitted in one SPI burst. The maximum length of a single SPI burst is defined in the BURST LENGTH field of the ECSPI_CONREG control register. (Figure 20-8 corresponds to a BURST LENGTH of 8.) This provides a way for transferring a longer SPI burst by writing data into TXFIFO while the ECSPI is transmitting.

 

 

But I did not find the ECSPI_PERIODREG register definition in spi-imx.c.

thanks

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