Regarding using the IPU as PCIe bus master: I'm interfacing with a FPGA FIFO implementation.
I'm assuming when a large buffer is DMA'd FROM the MX6 TO the FPGA FIFO the PCIe controller will fragment the buffer into packets consisting of the max amount of words the MX6 can support per TLP. The first fragment will be a write to the requested address and the next fragment will write to the initial address PLUS the previously written bytes; as-if the transfer was to a flat memory.
Question: Can the IPU/PCIe be configured to continually write to the same address without resorting to DMA buffers sized to the max words per TLP (eg. manual control of each transfer)?