I am using a MK21FX512VMC12 micro as the I2C master in a single master system. The bus has strong pullups.
We occasionally have seen the I2C master get stuck in a state where the busy bit becomes set and remains set. We have not yet captured the event happening, but afterward it remains in the stuck state until we power cycle. When it's sitting in the stuck state, we observe that the SCL and SDA lines are high. In this state our micro doesn't do any more i2c accesses because it (erroneously) thinks the bus is busy. Our master is running the I2C bus at a 100 kHz SCL frequency.
In this state the registers are as follows:
- A1: 12
- F: 1f
- C1: 88
- S: 21
- D: 63
- C2: 00
- FLT: 5f (we were experimenting with the max glitch filter - but we also got into this state with glitch filter set to 0)
- RA: 00
- SMB: 00
- A2: c2
- SLTH: 00
- SLTL: 00
PORTB_PCR0 and PORTB_PCR1: 00000220
Can you advise us on the logic that controls the busy bit? That will guide us as we try to reproduce and catch what's happening on the bus to get into that state. Can you also advise us on an algorithm to clear the busy bit?