We are trying to get the LS2084A processor to work with the TI DP83867E. Our design is based on and almost identical to the NXP BlueBox Mini, but the original Aquantia AQR107 PHYs have been replaced by the TI PHY using SGMII on the same SerDes lanes that the original PHYs used.
We are at the point where we can boot the system and access registers. Almost everything seems to be working EXCEPT the SGMII interface is not successfully auto-negotiating. (mdio read on extended register 37 returns 0 instead of 1). NOTE: They external interface to the PHYs is auto-negotiating successfully, and we are getting a good link status.
Our biggest point of confusion right now is just the instructions on accessing the LS2084A MDIO register space. According the the user manual we need to to set the SGMII Link Timer Registers (LINK_TMR_U=0h03 and LINK_TMR_L=0h06A0) among other things. The instructions to access these registers say “The SGMII MDIO register space is selected when the associated SGMIInCR1[MDEV_PORT] matches the Ethernet MAC PHY address (MDIO_CTL[PHY_ADDR]).”
I am trying to do all of this manually right now in U-boot to see if it works. However... I have no idea what this MDIO_CTL[PHY_ADDR] address is, and the manual does not seem to explain this anywhere. Am I missing something obvious? I can set the SGMIInCR1[MDEV_PORT] address no problem, but what is the MDIO_CTL[PHY_ADDR] which I need to set it too? I have tried just setting it to the PHY addresses which they are strapped to, but that doesn't seem to do anything.