SPDIF receiver loss of lock Issue

[kejieyu]

Hello,

Our system running on 48KHz sample rate.

Have a problem of SPDIF receiver loss of lock. Sometimes the loss of lock interrupt was set during SPDIF is working. and during the loss of RX clock, there are  lots of bit level errors such as below Log show.and after a while RX DPLL locked again,  and SPDIF working again.

So, Is there a hardware problem about the i.MX6Q embeded SPDIF soc?

or

Is there a way to improve this problem?

Becasue, sometimes, change the loss of lock  to re-locked seemly too long to bring audio problems.

Log:

SPDIF RX Sync Loss. Status Reg: 0x0000c614
SPDIF receiver found parity bit error. Status Reg: 0x0000c612
SPDIF receiver found illegal symbol. Status Reg: 0x0000c611
SPDIF receiver found illegal symbol. Status Reg: 0x00008612
SPDIF DPLL Locked. Status Reg: 0x00900610

Thanks.

[CarlosCasillas]

Hi,

Could you please specify which BSP version are you using? Is the problem present on a custom board, or it is also present on a NXP board?

Best regards!

/Carlos

[CarlosCasillas]

Hi,

You could check the voltage of the pin SPDIF_IN and adjust the pull-down/pull-up or driver strength. 

Hope this will be useful for you.

Best regards!

/Carlos

[kejieyu]

Hello,

It's on a custom board. and the SPDIF driver also developed by us on QNX.

Our system schematic like

i.MX6 < -> LVDS (DS90LV028A) <-- RJ45 CAT7 --> LVDS (DS90LV019T) <-> DIX4192

Do you means the voltage will impact the DPLL lock?  I will check the voltage and pull-down/pull-up and driver strength.

Do you know the sample rate on 48KHz the jitter is a problem or not ?

Thanks.

[CarlosCasillas]

Hi,

Yes. It seems that the signal quality is the point for the issue. So suggest to adjust the IOMUX.

Hope this will be useful for you.
Best regards!
/Carlos
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