I am working with a T2080 device and I need some help to understand the voltage level of some signals.
According to the datasheet of the microprocessor, the input voltage range of every SerDes signal, including clocks, is GND to SVDD (which is 1V).
But, in the reference design board, the serdes clock signals that go to the T2080 inputs (SD1_REFCLK1_P, SD_REFCLK1_N...) have a higher voltage level (2V5/3V3).
How can it be possible? Is the input voltage range higher for clock signals than for the rest of the serdes signals?
Thank you in advance.