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关于RT1052的以太网驱动问题

Question asked by 卢 鲲 on Apr 27, 2019
Latest reply on Apr 29, 2019 by jeremyzhou

尊敬的管理者,您好!

 

  我再开发RT1052时,发现了新旧两个版本的fsl_clock.h文件,其中关于以太网PLL配置的描述很不一样。我的开发是基于新版本的fsl,但是恰恰只有旧版本的fsl才能将以太网PLL配置成功。所以想求助各位高手,我该如何正确配置。

 

下面是两个版本的相关配置代码,谢谢!

 

旧版本:

typedef struct _clock_enet_pll_config
{
bool enableClkOutput0; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
bool enableClkOutput2; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */
uint8_t loopDivider0; /*!< Controls the frequency of the ENET0 reference clock.
b00 25MHz
b01 50MHz
b10 100MHz (not 50% duty cycle)
b11 125MHz */
uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock.
b00 25MHz
b01 50MHz
b10 100MHz (not 50% duty cycle)
b11 125MHz */
} clock_enet_pll_config_t;

 

void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
{
uint32_t enet_pll = CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(config->loopDivider1) |
CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(config->loopDivider0);

if (config->enableClkOutput0)
{
enet_pll |= CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK;
}

if (config->enableClkOutput1)
{
enet_pll |= CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK;
}

if (config->enableClkOutput2)
{
enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
}

CCM_ANALOG->PLL_ENET = enet_pll;

/* Wait for stable */
while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
{
}
}

//网络时钟配置
clock_enet_pll_config_t enet_pllconfig=
{
true, //使能ENET0时钟
false, //RT1052没有ENET1!
false, //RT1052没有ENET2!
1, //ENT0输出频率为50Mhz,采用RMII接口
1 //RT1052没有ENET1!
};

 

新版本:

/*! @brief PLL configuration for ENET */
typedef struct _clock_enet_pll_config
{
bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */

bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
b00 25MHz
b01 50MHz
b10 100MHz (not 50% duty cycle)
b11 125MHz */
uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */

} clock_enet_pll_config_t;

 

void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
{
uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider);

CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) |
CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src);

if (config->enableClkOutput)
{
enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
}

if (config->enableClkOutput25M)
{
enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
}

CCM_ANALOG->PLL_ENET =
(CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) |
enet_pll;

/* Wait for stable */
while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
{
}

/* Disable Bypass */
CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK;
}

 

//网络时钟配置
clock_enet_pll_config_t enet_pllconfig=
{
false, //使能ENET0时钟
true, //RT1052没有ENET1!
1, //ENT0输出频率为50Mhz,采用RMII接口
1 //RT1052没有ENET1!
};

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