We need to measure input frequency of about 30 MHz. The idea is to use IMX6ULL GPT2, clocked internally with the 24MHz IPG clock, and configure the input frequency pin JTAG_MOD (ie to be measured) as External Clock in GPT2_CR, and JTAG_TDO as GPT2_CAPTURE2.
The Reference Manual has a statement:
To ensure proper operations of GPT, the external clock input frequency should be less than 1/4 of frequency of the peripheral clock (ipg_clk).
Now the question: if we use the divider "4" set in GPT2_PR, to divide the input 30MHz to the safe value of (30/(4+1)) 6MHz, will that satisfy the "1/4" restriction above?