I have question about settings for DDR
The comments in the [Register Configuration] sheet J73 and J77 in the following file are described in the following two stages.
1st step: Settings other than PWDT_0 and PWDT_1
2nd step: PWDT_0, PWDT_1 settings
The reference manual does not contain instructions to set two levels, but does user need to set two steps ?
If necessary, please tell us how much time between 1st step and 2nd step should be left.
There are two registers that can set the ODT value of DRAM_DATA [63: 0]. When setting the ODT value, can you tell which register's ODT value will be reflected?
・IOMUX C_SW_PAD_CTL_GRP_TERM_CTL 0 to 7 [ODT] field
・MPODTCTRL ODTx_INT_RES field