AnsweredAssumed Answered

SSI TDM mode master clock configuration issue?

Question asked by Durgaprasad kolluri on Apr 21, 2019
Latest reply on Apr 22, 2019 by igorpadykov

Hi all,


I was new to SSI TDM mode. we are trying to interface 24-bit frame sync ADC to SSI lines in imx6 board. I had written driver for initialising the SSI in TDM mode. I could able to achieve interface is working. ADC is responding with data with two channels. 


Right now i was facing any sampling rate issue. I could able to generate master clock from SSI lines upto 12MHz and sampling rate(frame sync clock) 20Kbps. we want to configure the ssi master clock 24Mhz & sampling rate 48Khz.


anyone please tell me how to configure the master clock & sampling rate as per my need.


we are using yocto 4.9.88. please suggest me any solution to configure the master clock with required frequency.


I attached driver file below for all your reference.


Thanks in advance.


K. durgaprasad.