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MPC5777M SIUL2 IO config

Question asked by Bi weiping on Apr 20, 2019
Latest reply on Apr 23, 2019 by Petr Stancik

I have some questions for this problem:   https://community.nxp.com/thread/500624#comment-1140494 

 

when I set SIUL2 MSCR_IO register like this:

/* Configure pad PD14 for AF1 func: LIN2TX */
SIUL2.MSCR_IO[62].B.OERC = 3; /* Pad PD14: Maximum slew rate */
SIUL2.MSCR_IO[62].B.ODC = 2; /* Pad PD14: push-pull Output */
SIUL2.MSCR_IO[62].B.SSS = 2; /* Pad PD14: Source signal is LIN0_TXD */

but actually the result is not right as follow:

 

So I must set this register like this:

/* Configure pad PD14 for AF1 func: LIN2TX */
SIUL2.MSCR_IO[62].R = 0x32000002;

/* Configure pad PD15 for LIN0RX */
SIUL2.MSCR_IO[63].R = 0x0080000; /* Pad PD15: Enable pad for input - LIN2_RXD */
SIUL2.MSCR_MUX[850-512].R = 1; /* LIN2_RXD: connected to pad PD15 */

 

when I see MSCR_IO register table, I find a reserved bit before OERC.

 

My question is

1. how can I know which register can support bit setting or not? Reading reg bit can work well?

2. how does the reserved bit works when seting 0x32000002, Why OERC becomming 3?

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