I have a FPGA connected to an IMX6Q via PCIe that provides some registers. My questions center around multi-core FPGA register access. Admittedly I have not dug into the docs - I was hoping to leverage someone else's knowledge.
- Can two cores access 2 different registers of the FPGA simultaneously using mmap'd memory (Program IO)?
- What guarantees exclusive access? I'm guessing it's the NIC-301...
- Can a DMA operation to the registers occur simultaneously with a normal PIO without SW guaranteeing exclusivity?
- (Probably the same question as (1)) What happens when a thread that is actively doing a register read (PIO) is preempted/interrupted by another thread/ISR that also issues a PIO register read?