I am using iMX6 Dual lite processor, In which DDR3 we are doing the layout 4 DDR3 chips with Fly-by topology.
We are doing the Address,cmd and ctrl lines length matching tightly with clock pair and data byte with data mask and strobe tight length matching. Do we need to length match Data strobe also with respect to clock pair? because i noticed we have write and read leveling in DDR3
so,planning to adjust the write\read leveling instead of matching data strobe with respect to clock of each chip. is that works? also these write \read level adjustment should be done iMx6 or DDR chips?
Thanks and Regards