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ILI9881C device-tree modification

Question asked by Thinh Nguyen on Apr 10, 2019
Latest reply on Apr 10, 2019 by igorpadykov

I am working on MIPI pannel (panel-iliteck-ili9881). I back port the driver panel-iliteck-ili9881c.c from kernel 4.19 to kernel 4.9.88. Fortunately, I can compile and make this driver works (know this by adding debug log to driver). Now I get trouble at modifying device tree.

 

There are lots of clock definition. which value that I need to modified? how to calculate these clock value? 

 

Below is a part of  my device tree that I modified for new LCD pannel

 

&hdmi {
    status = "disabled";
};

&dcss {
    status = "okay";
    disp-dev = "mipi_disp";

    clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
         <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
         <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
         <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
         <&clk IMX8MQ_CLK_DUMMY>,
         <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
    clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";

    assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
             <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
             <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
             <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
             <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
             <&clk IMX8MQ_VIDEO_PLL1>;
    assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
                 <&clk IMX8MQ_SYS1_PLL_800M>,
                 <&clk IMX8MQ_SYS1_PLL_800M>,
                 <&clk IMX8MQ_CLK_25M>;
    assigned-clock-rates = <600000000>,
             <800000000>,
             <400000000>,
             <0>,
             <400000000>,
             <599999999>;

    dcss_disp0: port@0 {
        reg = <0>;
        dcss_disp0_mipi_dsi: mipi_dsi {
            remote-endpoint = <&mipi_dsi_in>;
        };
    };
};

&mipi_dsi_phy {
    status = "okay";
};

&mipi_dsi {
    status = "okay";
    assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
             <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
             <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
             <&clk IMX8MQ_VIDEO_PLL1>;
    assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
                 <&clk IMX8MQ_SYS1_PLL_266M>,
                 <&clk IMX8MQ_CLK_25M>;
    assigned-clock-rates = <24000000>,
             <266000000>,
             <0>,
             <599999999>;

    port@1 {
        mipi_dsi_in: endpoint {
            remote-endpoint = <&dcss_disp0_mipi_dsi>;
        };
    };

};

&mipi_dsi_bridge {
    status = "okay";

    panel@0 {
        compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
        reg = <0>;
        pinctrl-0 = <&pinctrl_mipi_dsi_en>;
        reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;

        // dsi-lanes = <4>;

        // panel-width-mm = <68>;
        // panel-height-mm = <121>;
    
        port {
            panel1_in: endpoint {
                remote-endpoint = <&mipi_dsi_bridge_out>;
            };
        };
    };

    port@1 {
        mipi_dsi_bridge_out: endpoint {
            remote-endpoint = <&panel1_in>;
        };
    };
};

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