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Strange Behavior of Coresight Module of i.MX 6SoloX SABRE Board

Question asked by HyunJun Kim on Apr 8, 2019
Latest reply on May 20, 2019 by Yuri Muhin

 My team is doing a project that uses PTM of ARM CoreSight Framework. We should get the branch trace from linux system inside the board with ETB. (Not using JTAG)

 We are using Cortex-A9 core only and trying with 4.14.78 linux-imx kernel from github / u-boot, root file system made from Yocto release.

 

 We could get a trace from the PTM, but it seems that result is abnormal. We followed these procedures described below.

 

 First, Referring this link - https://community.nxp.com/message/872513?commentID=872513#comment-872513

We edited device tree with the code inside the link. And changed reg address (referring to IMX6SXRM) and clock (to IMX6SX_CLK_AXI / also tested with IMX6SX_CLK_AHB)

 

 Next, we tried different versions of coresight drivers.

 

First, we tried with old coresight driver that composed of coresight.h, etm.c. Because we edited the code to configure PTM and other components' register, and succeeded to get PTM trace from the other board. After tracing procedure on sample program with PTM, we could get only 5 words output  from ETB. 

 

ffffffff
00800100
00000000
00000000
00000000

 

We tried to test with various values that we can set on PTM and other components' register, but all results were same.

 

We also tried with newer CoreSight driver that included in 4.14.78 without any register configuration. Trace in ETB was

 

21000000

00000180

00000000

00000008

and other fields were 0 in ETB.

 

Question is

 

1. Is there any other extra configuration to get normal trace? Such as clock that should be enabled or any other fundamental settings?

 

2. If we did right setting for tracing with PTM, It seems that PTM or ETB is malfunctioning.

 Especially ETB size is different from the size that written in IMX6SXRM. In the reference Manual, ETB's Trace RAM size is 2KB, but ETB's size register says ETB's size is 16KB. That is built- in constant that set from the RTL Design. So It makes me confused.

 

3. I want to know exact PTM's port size. It's not in the manual. I could know ETM of Cortex M4's Port Size is 8bit, but not PTM.

 

Please help us. We used almost a month to find out the solution.

I'm looking forward to expertise's sincere advise. Thank you

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