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i2s: MCLK signal

Question asked by Emilio Moretti on Apr 7, 2019
Latest reply on Apr 9, 2019 by Emilio Moretti

Hi, I set up a DMA to transfer data over I2S.0 in my lpc4337. Alsignals look OK (SCK, WS and SD), but the MCLK signal is only 1v, and it does NOT look square at all.


This is the output of a 20Mhz the oscilloscope I have at home:

500mV x 0.2uS


mclk signal is about 5mm of distance from the board pin and it can't get any closer. I used to have a protoboard with a lot of long cables, and the signal looked like the one below, but that's no longer the case.


MCLK and SCK with very long cables on a protoboard. 1V x 0.2uS.

Ignore this picture as this is no longer a problem.


Any tips on what may be going on?



I2S extra question

CS4335 protocol is i2s, left justified, MSB first. From their datasheet the data is valid on the first rising edge.


About shifting the bits with respect to frame edges. I believe this is called PCM typical format, while NOT shifting the bits is the typical i2s protocol. Out of curiosity, is there any way to do this in the LPC4337? And about being left justified, is there any way to set it up? Because I've been reading the Datasheet but I'm not able to find it.

So far I had to modify LPC open to change to big endianess, and enable MCLK, which was not possible with the existing examples.



Nevertheless the main issue for now is that I'm not being able to output a clean MCLK to power on the CS4335 as it requires MCLK and WS to power ON. (SCK is optional).



Thank you.