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LPIT0 Ch1 Interrupt.

Question asked by antonior soto on Apr 7, 2019
Latest reply on Apr 8, 2019 by antonior soto

Hello,

 

I need to configure LPIT0_CH1 in S32K144-QN57U, after some attempts I was not able to make it work, can anyone help me to review next configuration :

 

Thank you, Antonio.

 

#define LPIT0_BASE (0x40037000u)

#define LPIT0 ((LPIT_Type *)LPIT0_BASE)

 

void NVIC_init_IRQs (void) {
S32_NVIC->ICPR[1] = 1 << (49 % 32);
S32_NVIC->ISER[1] = 1 << (49 % 32);
S32_NVIC->IP[49] = 0xF0;
}

void LPIT0_init (void) {
PCC->PCCn[PCC_LPIT_INDEX] = PCC_PCCn_PCS(6);
PCC->PCCn[PCC_LPIT_INDEX] |= PCC_PCCn_CGC_MASK;
LPIT0->MCR = 0x00000001;
LPIT0->MIER = 0x00000010;
LPIT0->TMR[1].TVAL = 10000000;
LPIT0->TMR[1].TCTRL = 0x10000001;
}


void LPIT0_Ch1_IRQHandler (void) {
LPIT0->MSR |= LPIT_MSR_TIF1_MASK; /* Clear LPIT1 timer flag 0 */

PTD->PTOR |= 1<<LED_GREEN; /* Toggle output on port */
}

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