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DMA is not clearing SFR of SDADC after data transfer

Question asked by Michael Jihan on Apr 5, 2019
Latest reply on Apr 8, 2019 by David Tosenovjan

Hi,

So i have configured SDADC_1 and SDADC_4 to run in differential mode, and i have configured DMA_B to transfer data from SDADC_CDR to an array.

 

My Configuration DMA -

DMA_B_TCD36_SADDR FFE44020 SADDR FFE44020
DMA_B_TCD36_ATTR 0202 SMOD 00: Source address modulo feature is disabled
SSIZE 02: 32-bit
DMOD 00
DSIZE 02
DMA_B_TCD36_SOFF 0000 SOFF 0000
DMA_B_TCD36_NBYTES_MLNO 00000020 NBYTES 00000020
DMA_B_TCD36_NBYTES_MLOFFNO 00000020 SMLOE 00: The minor loop offset is not applied to the SADDR
DMLOE 00: The minor loop offset is not applied to the DADDR
NBYTES 00000020
DMA_B_TCD36_NBYTES_MLOFFYES 00000020 SMLOE 00: The minor loop offset is not applied to the SADDR
DMLOE 00: The minor loop offset is not applied to the DADDR
MLOFF 000000
NBYTES 0020
DMA_B_TCD36_SLAST 00000000 SLAST 00000000
DMA_B_TCD36_DADDR 400407B4 DADDR 400407B4
DMA_B_TCD36_CITER_ELINKYES D802 ELINK 01: The channel-to-channel linking is enabled
LINKCH 2C
CITER 0002
DMA_B_TCD36_CITER_ELINKNO D803 ELINK 01: The channel-to-channel linking is enabled
CITER 5801
DMA_B_TCD36_DOFF 0004 DOFF 0004
DMA_B_TCD36_DLASTSGA FFFFFF80 DLASTSGA FFFFFF80
DMA_B_TCD36_BITER_ELINKYES D804 ELINK 01: The channel-to-channel linking is enabled
LINKCH 2C
BITER 0004
DMA_B_TCD36_BITER_ELINKNO D804 ELINK 01: The channel-to-channel linking is enabled
BITER 5804
DMA_B_TCD36_CSR 2C20 BWC 00: No eDMA engine stalls
MAJORLINKCH 2C
DONE 00
ACTIVE 00
MAJORELINK 01: The channel-to-channel linking is enabled
ESG 00: The current channel's TCD is normal format
DREQ 00: The channel's ERQ {HL} bit is not affected
INTHALF 00: The half-point interrupt is disabled
INTMAJOR 00: The end-of-major loop interrupt is disabled
START 00: The channel is not explicitly started

 

 

 

DMA_B_TCD39_SADDR C3E48020 SADDR C3E48020
DMA_B_TCD39_ATTR 0202 SMOD 00: Source address modulo feature is disabled
SSIZE 02: 32-bit
DMOD 00
DSIZE 02
DMA_B_TCD39_SOFF 0000 SOFF 0000
DMA_B_TCD39_NBYTES_MLNO 00000020 NBYTES 00000020
DMA_B_TCD39_NBYTES_MLOFFNO 00000020 SMLOE 00: The minor loop offset is not applied to the SADDR
DMLOE 00: The minor loop offset is not applied to the DADDR
NBYTES 00000020
DMA_B_TCD39_NBYTES_MLOFFYES 00000020 SMLOE 00: The minor loop offset is not applied to the SADDR
DMLOE 00: The minor loop offset is not applied to the DADDR
MLOFF 000000
NBYTES 0020
DMA_B_TCD39_SLAST 00000000 SLAST 00000000
DMA_B_TCD39_DADDR 40040914 DADDR 40040914
DMA_B_TCD39_CITER_ELINKYES 0002 ELINK 00: The channel-to-channel linking is disabled
LINKCH 00
CITER 0002
DMA_B_TCD39_CITER_ELINKNO 0003 ELINK 00: The channel-to-channel linking is disabled
CITER 0003
DMA_B_TCD39_DOFF 0004 DOFF 0004
DMA_B_TCD39_DLASTSGA FFFFFF80 DLASTSGA FFFFFF80
DMA_B_TCD39_BITER_ELINKYES 0004 ELINK 00: The channel-to-channel linking is disabled
LINKCH 00
BITER 0004
DMA_B_TCD39_BITER_ELINKNO 0004 ELINK 00: The channel-to-channel linking is disabled
BITER 0004
DMA_B_TCD39_CSR 0000 BWC 00: No eDMA engine stalls
MAJORLINKCH 00
DONE 00
ACTIVE 00
MAJORELINK 00: The channel-to-channel linking is disabled
ESG 00: The current channel's TCD is normal format
DREQ 00: The channel's ERQ {HL} bit is not affected
INTHALF 00: The half-point interrupt is disabled
INTMAJOR 00: The end-of-major loop interrupt is disabled
START 00: The channel is not explicitly started

 

 

 

My Configuration SDADC -

SDADC_1
SDADC_1_MCR 00011001 PDR 00: OSR = 24
PGAN 00: Gain = 1
HPFEN 01: High-pass (DC removal) filter is enabled
WDGEN 00: WDG is disabled
TRIGEDSEL 00: Falling edge of trigger input is selected
TRIGEN 01: Trigger input is enabled
TRIGSEL 00: Input trigger 0 is selected
FRZ 00: Conversions are not stopped
VCOMSEL 00: Negative input terminal is biased with VREFN
WRMODE 00: Wraparound mechanism disabled (in this case the default software control mechanism will be enabled)
GECEN 00: Gain error calibration mode disabled
MODE 00: Differential input mode selected
EN 01: SDADC internal modulator enabled
SDADC_1_CSR 00000000 BIASEN 00
ANCHSEL_WRAP 00
ANCHSEL 00
SDADC_1_RKR 0000A50F RESET_KEY A50F
SDADC_1_SFR 00000004 ANCHSEL_CNT 00
DFEF 00: Data FIFO is not empty
WTHH 00: Watchdog Upper Threshold Cross Over Event did not occur
WTHL 00: Watchdog Lower Threshold Cross Over Event did not occur
CDVF 01: Data output from SDADC is valid
DFORF 00: No overrun has occurred since the last time the flag was cleared
DFFF 00: The number of datawords in FIFO is less than the number indicated by FCR[FTHLD]
SDADC_1_RSER 00010001 WTHDIRS 00: Interrupt request is selected
DFFDIRS 01: DMA request is selected
GDIGE 00: No impact of external gating signal on module DMA/interrupt requests
WTHDIRE 00: Interrupt/DMA request is disabled on WDG Threshold Cross Over Event
CDVEE 00: Event output disabled
DFORIE 00: Interrupt request is disabled when data FIFO overrun condition occurs
DFFDIRE 01: Interrupt/DMA request is enabled when data FIFO full condition occurs
SDADC_1_OSDR 00000001 OSD 01
SDADC_1_FCR 00000807 FRST 00: No effect
FTHLD 08
FOWEN 00: Data FIFO OW option disabled
FSIZE 03: FIFO depth = 16 datawords
FE 01: Data FIFO is enabled; FIFO depth is indicated by FSIZE
SDADC_1_STKR 00000000 ST_KEY 0000
SDADC_1_CDR 0000FFFA CDATA FFFA
SDADC_1_WTHHLR 00000000 THRH 0000
THRL 0000

 

 

 

SDADC_4
SDADC_4_MCR 00013001 PDR 00: OSR = 24
PGAN 00: Gain = 1
HPFEN 01: High-pass (DC removal) filter is enabled
WDGEN 00: WDG is disabled
TRIGEDSEL 01: Rising edge of trigger input is selected
TRIGEN 01: Trigger input is enabled
TRIGSEL 00: Input trigger 0 is selected
FRZ 00: Conversions are not stopped
VCOMSEL 00: Negative input terminal is biased with VREFN
WRMODE 00: Wraparound mechanism disabled (in this case the default software control mechanism will be enabled)
GECEN 00: Gain error calibration mode disabled
MODE 00: Differential input mode selected
EN 01: SDADC internal modulator enabled
SDADC_4_CSR 00000000 BIASEN 00
ANCHSEL_WRAP 00
ANCHSEL 00
SDADC_4_RKR 0000A50F RESET_KEY A50F
SDADC_4_SFR 00000004 ANCHSEL_CNT 00
DFEF 00: Data FIFO is not empty
WTHH 00: Watchdog Upper Threshold Cross Over Event did not occur
WTHL 00: Watchdog Lower Threshold Cross Over Event did not occur
CDVF 01: Data output from SDADC is valid
DFORF 00: No overrun has occurred since the last time the flag was cleared
DFFF 00: The number of datawords in FIFO is less than the number indicated by FCR[FTHLD]
SDADC_4_RSER 00010001 WTHDIRS 00: Interrupt request is selected
DFFDIRS 01: DMA request is selected
GDIGE 00: No impact of external gating signal on module DMA/interrupt requests
WTHDIRE 00: Interrupt/DMA request is disabled on WDG Threshold Cross Over Event
CDVEE 00: Event output disabled
DFORIE 00: Interrupt request is disabled when data FIFO overrun condition occurs
DFFDIRE 01: Interrupt/DMA request is enabled when data FIFO full condition occurs
SDADC_4_OSDR 00000001 OSD 01
SDADC_4_FCR 00000807 FRST 00: No effect
FTHLD 08
FOWEN 00: Data FIFO OW option disabled
FSIZE 03: FIFO depth = 16 datawords
FE 01: Data FIFO is enabled; FIFO depth is indicated by FSIZE
SDADC_4_STKR 00000000 ST_KEY 0000
SDADC_4_CDR 00000003 CDATA 0003
SDADC_4_WTHHLR 00000000 THRH 0000
THRL 0000

 

 

i read in the manual that after dma transfer the data from cdr it automatically clears the SDADC_SFR register so that next conversion result can be recieved but its not happening in my case. i am having to manually clear the SDADC_SFR Register .WHY??  Please Help

 

Thank You

 

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