L JX

LPC54018  using emc with sdram for high frequrence

Discussion created by L JX on Apr 1, 2019
Latest reply on Apr 3, 2019 by L JX

Hello everyone. I need to run the code in sdram ,but i have some question.

MCU: LPC54018

DDR:IS42S16160J

when the frequence of EMC is lower than 90M HZ, SDRAM_DataBusCheck and  SDRAM_AddressBusCheck are boss OK.However, when the frequence of emc is higher than 90M, SDRAM_DataBusCheck is ok but  SDRAM_AddressBusCheck is not.

I find a comment in sdk example that "if you change the divide to 0 and emc clock is larger than 100M, please take refer to emc.dox to adjust EMC clock delay". So i find a register named "EMCDYCCTRL" in MCU datasheet and try to adjust it. The EMCDYCCTRL[4:0] is used to adjust programmable delay value for EMC outputs in command delayed mode, the reset value is 0x10,and when i adjust it to 0x08, the sdram can pass the test in 96M HZ, and when i adjust it to 0x04, the sdram can pass the test in 108M Hz. However, when i adjust the value to 0x00, sdram can't pass the test in 120M HZ. And when i run the same code(90M and 108M) in the other boards , it is unstable.

There is another register of mcu named "EMCCAL", which allows calibration of the EMC programmbable delays by providing a real-time representation of the value of those delays.Delay settings that are in use in the appication can be calibrated to compensate for intrinsic differences between devices, and for changes in ambient conditons.it reurns the count of the approximately 50MHz ring oscillator that occur during 32 clocks of the FRO 12MHz. This represents the composite effect of processing variation,internal regulator supply voltage, and ambient temperature. 

 

I have some questions:

why i need to adjust the EMCDLYCTRL register when the frequence of emc is larger than 90MHz?

what's the connection of EMCDLYCTRL  and EMCCAL ? whether i need to adjust the EMCDLYCTRL according to the returns of EMCCAL?

when i read the returns of the EMCCAL (EMCCAL [7:0]),the value is 0x234, but the standard value should be 134, if it is too large?

why the sdram is unstable when i run the same code in another boards, should i adjust the EMCDYCCTRL  again according to the EMCCAL of this boards?

 

Thanks for alls .

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