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why there is a large gap among DMA transfers (LPSPI)

Question asked by david_geng on Mar 31, 2019
Latest reply on Apr 1, 2019 by Hui_Ma

Hi, 

 

I'm testing the maximum speed of the LPSPI port on a RT1021 board. I downloaded the official cmsis_lpspi_edma_b2b_transfer_master example and only changed the port to LPSPI3 and SPI clock to 50MHz. I just get 25MHz actually, but that's ok.

 

However, one thing slows the transfer down is that there appears to be a rather large gap (about 1us) among each transfer. So why is that during a DMA process? any chance to remove such limitation? 

 

Many thanks,

 

David

 

PS. enclosed the waveform captured

 

LPSPI waveform

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