Dear colleagues and NXP technical support,
I can't figure out the length of page read access for NOR flash by LS1043A's IFC (IFC_CSORn_NOR[PGRD_EN] = 1). How can a software affect the burst size? Or is it fixed?
I have read the Introduction to Integrated Flash Controller and a Comparison with Enhanced Local Bus Controller and it seems the burst size is determined by the cache line size and as I understand the Cortex-A53's cache line size is 64B, so in the end, IFC performs 64B long page reads. Is this fixed or can software change the 64B to lower value, especially 32B?
I'm asking because all parallel NOR flashes we've found have 32B page size, even for example MT28EW used in LS1043A-RDB, so if 64B was fixed value, it would cause IFC in LS1043A unusable for page access with most flashes and this really seems like wrong reasoning from our side.
In LS1043A's reference manual there is explanation based on system bus' multi-beat transactions, but to be honest, I do not understand ARM's internal architecture enough to understand that. Please, can anyone simplify this explanation?