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iMX RT1062 SDK LCD clocking

Question asked by Mike Spenard on Mar 27, 2019
Latest reply on Mar 28, 2019 by Mike Spenard

I'm using NXP's iMX RT1062 eval kit with the Rocktech 4" LCD. I have a SDK question related to the fsl_elcdif example code. Specifically how the LCD gets clocked. 

 

Why do your comment say 93Mhz for PLL clock rate when the Rocktech display runs at 9.3Mhz. Why the factor of 10?

Here's your full comments:

 

void BOARD_InitLcdifPixelClock(void)
{

    /*
     * The desired output frame rate is 60Hz. So the pixel clock frequency [for RockTech] is:
     * (480 + 41 + 4 + 18) * (272 + 10 + 4 + 2) * 60 = 9.2M.
     * Here set the LCDIF pixel clock to 9.3M.
     */

    /*
     * Initialize the Video PLL.
     * Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz.
     */


   clock_video_pll_config_t config = {
           .loopDivider = 31, .postDivider = 8, .numerator = 0, .denominator = 0,
       };  
    CLOCK_InitVideoPll(&config);

 

..

}

 

Your first comment block spells out the math behind and goal of 9.3mhz (which is the LCD's sync rate). But then your PLL code states the goal is 93mhz. So why the factor of 10 increase?

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