We have one of your sabre development boards with the IMX7 dual processor populated. We are using it to prove the bsdl model supplied prior to a mutual customers production run.
Some of the IO pins follow the BSDL and can be toggled when the device is in boundary-scan/extest mode.
However none of the DDR pins (Address/data/control) toggle - they sit at 0.5V during test.
Is there any configuration (board or chip) required to turn on the ddr bank so the IMX7's "DDR" address/data and control pins toggle in extest?
(eg, IMX6 did have a register which needed programming to turn the EIM bus from highz drive value).