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DDR calibration on LS1012A

Question asked by Mauro Moioli on Mar 26, 2019
Latest reply on Apr 4, 2019 by Bulat Karymov

Hi all,

we are investigating a problem on a pre-production of 100 boards equipped with LS1012A that is consuming our time and delaying the production.

In particular we have some boards (about 20%) that hangs on boot exactly when uboot goes into DDR RAM.

 

By printing the DDR calibration results, we see that when fail happens a different value on mpdgctrl0 register, OFFSET1 is returned by the calibration phase.

 

To be more exact what we see is:

mpdgctrl0 OFFSET1 value: between 27 and 29 on correct boot (bit9: 0011011 :bit15 to bit9: 0011101 :bit15);

mpdgctrl0 OFFSET1 value: unpredictable but fixed to 0, 7 or 96 on hanging condition (0000000, 0000011, 1100000);

 

Please note that boards not OK, hang ONLY on 10% of the boot, with highest probability at first boot (when they are cold). If the board is able to start, it will NEVER hang during normal operation on main SW.

 

If we force a new calibration cycle as soon as we see uncorrect values, the board in any case has unpredictable results (that means: if we need to redo the calibration the board can hang or start, even if we reach a "good" OFFSET1 value).

 

Is there somebody that could help us or explain what can be the physical issue (bad DDR, bad soldering, ....)?

 

Thanks in advance.

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