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S32K144 CAN FD issue

Question asked by lei liu on Mar 26, 2019
Latest reply on Mar 27, 2019 by Petr Stancik

Hello
I would like to receive CAN FD Standard ID using Filter.

 

An ID (0x100 ~ 0x6FF) exists in the bus
I try to receive each filter using different filters from 0x100 to 0x1FF, 0x200 to 0x2FF, 0x300 to 0x3FF, 0x400 to 0x4FF, 0x500 to 0x5FF, and 0x600 to 0x6FF for each filter.

Below is my code:

{
#define MBR0_BASE ((unsigned char *)0x40024080)

#define PL_LEN_8 16
#define PL_LEN_16 24
#define PL_LEN_32 40
#define PL_LEN_64 72

#define CAN0_MBR0(pl, idx) ((MB_Struct*)((MBR0_BASE) + (PL_LEN_##pl) * (idx)))
unsigned long i;

/* Activate Clock for FlexCAN and PORT */
PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK;
if(portn == PTE4_PTE5_CAN)
{
PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK;
PORTE->PCR[4] |= PORT_PCR_MUX(5);
PORTE->PCR[5] |= PORT_PCR_MUX(5);
}
else if(portn == PTC2_PTC3_CAN)
{
PCC->PCCn[PCC_PORTC_INDEX] |= PCC_PCCn_CGC_MASK;
PORTC->PCR[2] |= PORT_PCR_MUX(3);
PORTC->PCR[3] |= PORT_PCR_MUX(3);
}

CAN0->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */

CAN0->CTRL1 |= CAN_CTRL1_CLKSRC_MASK; /* CLKSRC=1: Clock Source = BUSCLK (40 MHz) */

CAN0->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/

while (!((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {}

/* Good practice: wait for FRZACK=1 on freeze mode entry/exit */

CAN0->CBT = 0x802FB9EF; /* Configure nominal phase: 500 KHz bit time, 40 MHz Sclock */

/* Prescaler = CANCLK / Sclock = 80 MHz / 40 MHz = 2 */

/* EPRESDIV = Prescaler - 1 = 2 - 1 = 1 */

/* EPSEG2 = 15 */

/* EPSEG1 = 15 */

/* EPROPSEG = 46 */

/* ERJW = 15 */

/* EPRESDIV= 3 CAN0->CBT= 0x80685CE7 koor*/

/* BITRATEn =Fcanclk /( [(1 + (EPSEG1+1) + (EPSEG2+1) + (EPROPSEG + 1)] x (EPRESDIV+1)) */

/* = 80 MHz /( [(1 + ( 15 +1) + ( 15 +1) + ( 46 + 1)] x ( 1 +1)) */

/* = 80 MHz /( [1+16+16+47] x 2) = 80 MHz /(80x2) = 500 Kz */

CAN0->FDCBT = 0x00131CE3; /* Configure data phase: 2 MHz bit time, 40 MHz Sclock */

/* Prescaler = CANCLK / Sclock = 80 MHz / 40 MHz = 2 */

/* FPRESDIV = Prescaler - 1 = = 2 - 1 = 1 */

/* FPSEG2 = 3 */

/* FPSEG1 = 7 */

/* FPROPSEG = 7 */

/* FRJW = 3 */

/* BITRATEf =Fcanclk /( [(1 + (FPSEG1+1) + (FPSEG2+1) + (FPROPSEG)] x (FPRESDIV+!)) */

/* = 80 MHz /( [(1 + ( 7 +1) + ( 3 +1) + ( 7 )] x ( 1 +1)) */

/* = 80 MHz /( [1+8+4+7] x 2) = 80 MHz /(20x2) = 80 MHz / 40 = 2 MHz */

CAN0->FDCTRL =0x80030500; /* Configure bit rate switch, data size, transcv'r delay */

/* BRS=1: enable Bit Rate Swtich in frame's header */

/* MBDSR1: Not applicable */

/* MBDSR0=3: Region 0 has 64 bytes data in frame's payload */

/* TDCEN=0: disable Transceiver Delay Compensation */

/* TDCOFF=5: 5 CAN clocks (300us) offset used */


for (i=0; i<7; i++)
{
CAN0_MBR0(64, i)->CS.R = 0;
CAN0_MBR0(64, i)->ID.R = 0;
}
for(i=0; i<16; i++ ) /* Initialize all of 16 Individual Filter Mask */
{
CAN0->RXIMR[i] = 0x1FFFFFFF; /* Disable Filter Mask */
}

CAN0_MBR0(64, 2)->CS.B.EDL = 1; /* 1: CAN FD frame */
CAN0_MBR0(64, 2)->CS.B.BRS = 1; /* 1: CAN FD frame Bode Rate Switch Enable */
CAN0_MBR0(64, 2)->CS.B.IDE = 0; /* Use standard ID length */
CAN0_MBR0(64, 2)->ID.B.ID_STD = 0x10; /* receive ID is 0x123 */
CAN0_MBR0(64, 2)->CS.B.CODE = 0x4;

CAN0->RXMGMASK = 0x1FFFFFFF;//0x1FFFFFFF; /* Global acceptance mask */
CAN0->IMASK1 = 0x0000000E; /* MB 3 for CAN0 interrupt Enable */

 

 

CAN0->CTRL2 |=CAN_CTRL2_ISOCANFDEN_MASK; /* Enable CRC fix for ISO CAN FD */

CAN0->MCR = 0x0002081F;//0x0002081F; /* Negate FlexCAN 1 halt state & enable CAN FD for 32 MBs */

while ((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {}

/* Good practice: wait for FRZACK to clear (not in freeze mode) */

while ((CAN0->MCR & CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {}


INT_SYS_EnableIRQ(CAN0_ORed_0_15_MB_IRQn);
}

Outcomes