We are using AOIP DDR in LS2088A custom board, we are planing for data bus bit swapping. Do we need to change code in DP DDR for swapping.
> we are planing for data bus bit swapping.
Is the mentioned swapping described in the QorIQ LS2088A Reference Manual, 12.5.49 DQ mapping register 0 (DDR_DQ_MAP0)?
If "yes", then this is an internal DDR controller data processing, which is not visible to the application software.
We are doing bit swapping in DDR_DQ_MAP3 for AOIP DDR. all nibble values are available Table 12-7 is that enough for AOIP DDR or we need to do configuration changes.
> We are doing bit swapping in DDR_DQ_MAP3 for AOIP DDR
What do you mean?
Are you talking about the DPAA2 Dedicated DRAM Controller?
Please consider that it has 32-bit data bus and DDR_DQ_MAP3 can not be used - it contains DQ_60_63 ECC_0_3 ECC_4_7.
Thank you for clarification. Any software changes for DPAA2 Dedicated DRAM Controller. and any DP_DDR need to configure for bit swapping in DPAA2 DRAM.
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