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MPC5744P SPI TX problem

Question asked by Mark Lukek on Mar 23, 2019
Latest reply on Mar 25, 2019 by Petr Stancik

Hello,

 

I want to send some data (0xF0F0) with SPI on MPC5744P, but there is no activity on any of the signals (CLK, CS, MISO or MOSI). Am I doing something wrong? If I understand correctly, after write to PUSHR there should be something in the TXFR registers, but there isn't.

 

void SysClk_Init(void)
{
MC_CGM.AC3_SC.R = 0x01000000; //Connect XOSC to the PLL0 input.
MC_CGM.AC4_SC.R = 0x03000000; //Connect PLL0_PHI1 to the PLL1 input.

//Set PLL0 to 160 MHz with 40 MHz XOSC reference.
PLLDIG.PLL0DV.R = 0x40024020; //PREDIV = 4, MFD = 32, RFDPHI = 2, RFDPHI1 = 8

MC_ME.RUN0_MC.R = 0x00130070; // RUN0 cfg: IRCON,XOSCON,PLL0ON,syclk=IRC

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode

//Set PLL1 to 200 MHz with 40 MHz PLL0_PHI1 input.
PLLDIG.PLL1DV.R = 0x00020014; //MFD = 20, RFDPHI = 2
PLLDIG.PLL1FD.R = 0x00000000; //EnableandconfigurationfractionalmultiplierforPLL1

MC_ME.RUN_PC[0].R = 0x000000FE; //Enable peripherals to run in all modes
MC_ME.RUN0_MC.R = 0x001300F4; // RUN0 cfg: IRCON, XOSCON, PLL0ON, PLL1ON, syclk=PLL1_PHI

MC_CGM.SC_DC0.R = 0x80030000; //Divide system clock by 4 to achieve PBRIDGEx_CLK of 50 MHz

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode
}

void InitPeriClkGen(void)
{
MC_CGM.SC_DC0.R = 0x80030000; //PBRIDGEx_CLK at system clock divided by 4 (50 MHz).
MC_CGM.AC0_SC.R = 0x02000000; //Select PLL0_PHI as source of Auxiliary Clock 0.
MC_CGM.AC0_DC0.R = 0x80000000; //MOTC_CLK: Enabled at Auxiliary Clock 0 divide by 1(160 MHz).
MC_CGM.AC0_DC1.R = 0x80070000; //SGEN_CLK: Enabled at Auxiliary Clock 0 divide by 8(20 MHz).
MC_CGM.AC0_DC2.R = 0x80010000; //ADC_CLK: Enabled at Auxiliary Clock 0 divide by 2(80 MHz).

/* Auxiliary Clock 1 is always sourced from PLL0_PHI. */
MC_CGM.AC1_DC0.R = 0x80010000; //FRAY_CLK: Enabled at Auxiliary Clock 1 divided by 2 (40 MHz).
MC_CGM.AC1_DC1.R = 0x80010000; //SENT_CLK: Enabled at Auxiliary Clock 1 divided by 2 (80 MHz).

/* Auxiliary Clock 2 is always sourced from PLL0_PHI. */
MC_CGM.AC2_DC0.R = 0x80010000; //CAN_CLK: Enabled at Auxiliary Clock 2 divided by 2 (40 MHz).

MC_CGM.AC5_SC.R = 0x02000000; //Select PLL0_PHI as source of Auxiliary Clock 5.
MC_CGM.AC5_DC0.R = 0x80070000; //LFAST_PLL: Enabled at Auxiliary Clock 5 divided by 8 (20 MHz).

MC_CGM.AC6_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 6.
MC_CGM.AC6_DC0.R = 0x80000000; //CLKOUT0: Enabled at Auxiliary Clock 6 divided by 1 (200 MHz).

MC_CGM.AC10_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 10.
MC_CGM.AC10_DC0.R = 0x80030000; //ENET_CLK: Enabled at Auxiliary Clock 10 divided by 4 (50 MHz).

MC_CGM.AC11_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 11.
MC_CGM.AC11_DC0.R = 0x80030000; //ENET_TIME_CLK: Enabled at Auxiliary Clock 10 divided by 4 (50 MHz).

/* DSPI 0 */
MC_ME.PCTL99.B.RUN_CFG = 0x0;
}

 

void SPI()

{

// chip select
SIUL2.MSCR[MSCR_SPI_CS].B.SSS = 1;
SIUL2.MSCR[MSCR_SPI_CS].B.OBE = 1;
SIUL2.MSCR[MSCR_SPI_CS].B.SRC = 3;
// clock
SIUL2.MSCR[MSCR_SPI_CLK].B.SSS = 1;
SIUL2.MSCR[MSCR_SPI_CLK].B.OBE = 1;
SIUL2.MSCR[MSCR_SPI_CLK].B.SRC = 3;
// MOSI
SIUL2.MSCR[MSCR_SPI_MOSI].B.SSS = 1;
SIUL2.MSCR[MSCR_SPI_MOSI].B.OBE = 1;
SIUL2.MSCR[MSCR_SPI_MOSI].B.SRC = 3;
// MISO
SIUL2.MSCR[MSCR_SPI_MISO].B.IBE = 1;
SIUL2.IMCR[IMCR_SPI_MISO].B.SSS = 1;

 

SPI_0.MCR.B.MSTR = 1;
SPI_0.MCR.B.DCONF = 0x0;
SPI_0.MCR.B.FRZ = 0;
SPI_0.MCR.B.PCSIS = 0x01;
SPI_0.MCR.B.HALT = 1;

 

SPI_0.MODE.CTAR[0].B.DBR = 0;
SPI_0.MODE.CTAR[0].B.FMSZ = 0xF;
SPI_0.MODE.CTAR[0].B.CPOL = 0;
SPI_0.MODE.CTAR[0].B.CPHA = 0;
SPI_0.MODE.CTAR[0].B.LSBFE = 0; // MSB first
SPI_0.MODE.CTAR[0].B.PBR = 0;
SPI_0.MCR.B.HALT = 0; // start module

 

SPI_0.PUSHR.PUSHR.R = 0x0801F0F0; // EOQ=1, PCS=1, TXDATA=0xF0F0

uint16_t tx_command = SPI_0.TXFR[4].B.TXCMD_TXDATA;
uint16_t tx_data = SPI_0.TXFR[4].B.TXDATA;

}

Outcomes