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Assigning a new input pin to FRDM-KW41Z project via MCUXpresso not working

Question asked by Colin Gerrish on Mar 22, 2019
Latest reply on Mar 29, 2019 by Estephania Martinez

I am new to MCUXpresso and I am learning with two FRDM boards. I have an FRDM-KL25 board and an FRDM-KW41Z board.

 

I started by downloading the GPIO_LED_OUTPUT driver project for each board. Both work as expected.

 

I then decided to assign a new GPIO pin as an INPUT using the Pins config tool.

 

In both cases, I chose the same pin.

 

So, for the FRDM-KL25 board, I chose pin no. 33 (GPIOA) which is labelled as J2[2]/D8. 

And for the FRDM-KW41Z board, I chose pin no. 1 (GPIOA) which is labelled as J2[1]/J9[2]/D8/SWD_DIO

 

Attributes were as follows:

- Direction: INPUT

- GPIO Interrupt: Interrupt on Falling edge

- Slew Rate: FAST

- Pull Select: Pullup

- Pull Enabled: Enabled

 

I use the same Identifier "NEW_IO" for both cases and I then click on "Update Project". 

 

I return to the development page and build the projects. All is fine so far.

 

Now, this is where it diverges in terms of success.

 

When clicking on DEBUG, the FRDM-KL25 works perfectly.

 

When clicking on DEBUG, the FRDM-KW41Z board crashes when trying to run the BOARD_InitPins(void) function.

 

The code for that function appears the same in each case.

 

Here is code for FRDM-KL25 board

 

/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
  - {pin_num: '28', peripheral: UART0, signal: TX, pin_signal: TSI0_CH3/PTA2/UART0_TX/TPM2_CH1}
  - {pin_num: '27', peripheral: UART0, signal: RX, pin_signal: TSI0_CH2/PTA1/UART0_RX/TPM2_CH0}
  - {pin_num: '53', peripheral: GPIOB, signal: 'GPIO, 18', pin_signal: TSI0_CH11/PTB18/TPM2_CH0}
  - {pin_num: '33', peripheral: GPIOA, signal: 'GPIO, 13', pin_signal: PTA13/TPM1_CH1, direction: INPUT, gpio_interrupt: kPORT_InterruptFallingEdge, pull_select: up,
    pull_enable: enable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/

/* clang-format on */

/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description   : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/

void BOARD_InitPins(void)
{
    /* Port A Clock Gate Control: Clock enabled */
    CLOCK_EnableClock(kCLOCK_PortA);
    /* Port B Clock Gate Control: Clock enabled */
    CLOCK_EnableClock(kCLOCK_PortB);

    gpio_pin_config_t NEW_IO_config = {
        .pinDirection = kGPIO_DigitalInput,
        .outputLogic = 0U
    };
    /* Initialize GPIO functionality on pin PTA13 (pin 33)  */
    GPIO_PinInit(BOARD_INITPINS_NEW_IO_GPIO, BOARD_INITPINS_NEW_IO_PIN, &NEW_IO_config);

    /* PORTA1 (pin 27) is configured as UART0_RX */
    PORT_SetPinMux(BOARD_INITPINS_DEBUG_UART_RX_PORT, BOARD_INITPINS_DEBUG_UART_RX_PIN, kPORT_MuxAlt2);

    const port_pin_config_t NEW_IO = {/* Internal pull-up resistor is enabled */
                                      kPORT_PullUp,
                                      /* Slow slew rate is configured */
                                      kPORT_SlowSlewRate,
                                      /* Passive filter is disabled */
                                      kPORT_PassiveFilterDisable,
                                      /* Low drive strength is configured */
                                      kPORT_LowDriveStrength,
                                      /* Pin is configured as PTA13 */
                                      kPORT_MuxAsGpio};
    /* PORTA13 (pin 33) is configured as PTA13 */
    PORT_SetPinConfig(BOARD_INITPINS_NEW_IO_PORT, BOARD_INITPINS_NEW_IO_PIN, &NEW_IO);

    /* Interrupt configuration on PORTA13 (pin 33): Interrupt on falling edge */
    PORT_SetPinInterruptConfig(BOARD_INITPINS_NEW_IO_PORT, BOARD_INITPINS_NEW_IO_PIN, kPORT_InterruptFallingEdge);

    /* PORTA2 (pin 28) is configured as UART0_TX */
    PORT_SetPinMux(BOARD_INITPINS_DEBUG_UART_TX_PORT, BOARD_INITPINS_DEBUG_UART_TX_PIN, kPORT_MuxAlt2);

    /* PORTB18 (pin 53) is configured as PTB18 */
    PORT_SetPinMux(BOARD_INITPINS_LED_RED_PORT, BOARD_INITPINS_LED_RED_PIN, kPORT_MuxAsGpio);

    SIM->SOPT5 = ((SIM->SOPT5 &
                   /* Mask bits to zero which are setting */
                   (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK)))

                  /* UART0 transmit data source select: UART0_TX pin. */
                  | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX)

                  /* UART0 receive data source select: UART0_RX pin. */
                  | SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX));
}

 

and here is the code for the FRDM-KW41Z board

 

/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
  - {pin_num: '42', peripheral: LPUART0, signal: RX, pin_signal: TSI0_CH2/PTC6/LLWU_P14/XTAL_OUT_EN/I2C1_SCL/UART0_RX/TPM2_CH0/BSM_FRAME}
  - {pin_num: '43', peripheral: LPUART0, signal: TX, pin_signal: TSI0_CH3/PTC7/LLWU_P15/SPI0_PCS2/I2C1_SDA/UART0_TX/TPM2_CH1/BSM_DATA}
  - {pin_num: '37', peripheral: GPIOC, signal: 'GPIO, 1', pin_signal: PTC1/ANT_B/I2C0_SDA/UART0_RTS_b/TPM0_CH2/BLE_RF_ACTIVE}
  - {pin_num: '1', peripheral: GPIOA, signal: 'GPIO, 0', pin_signal: TSI0_CH8/PTA0/SPI0_PCS1/TPM1_CH0/SWD_DIO, direction: INPUT, gpio_interrupt: kPORT_InterruptFallingEdge,
    slew_rate: fast, pull_select: up, pull_enable: enable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/

/* clang-format on */

/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description   : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/

void BOARD_InitPins(void)
{
    /* Port A Clock Gate Control: Clock enabled */
    CLOCK_EnableClock(kCLOCK_PortA);
    /* Port C Clock Gate Control: Clock enabled */
    CLOCK_EnableClock(kCLOCK_PortC);

    gpio_pin_config_t NEW_IO_config = {
        .pinDirection = kGPIO_DigitalInput,
        .outputLogic = 0U
    };
    /* Initialize GPIO functionality on pin PTA0 (pin 1)  */
    GPIO_PinInit(BOARD_INITPINS_NEW_IO_GPIO, BOARD_INITPINS_NEW_IO_PIN, &NEW_IO_config);

    const port_pin_config_t NEW_IO = {/* Internal pull-up resistor is enabled */
                                      kPORT_PullUp,
                                      /* Fast slew rate is configured */
                                      kPORT_FastSlewRate,
                                      /* Passive filter is disabled */
                                      kPORT_PassiveFilterDisable,
                                      /* Low drive strength is configured */
                                      kPORT_LowDriveStrength,
                                      /* Pin is configured as PTA0 */
                                      kPORT_MuxAsGpio};
    /* PORTA0 (pin 1) is configured as PTA0 */
    PORT_SetPinConfig(BOARD_INITPINS_NEW_IO_PORT, BOARD_INITPINS_NEW_IO_PIN, &NEW_IO);

    /* Interrupt configuration on PORTA0 (pin 1): Interrupt on falling edge */
    PORT_SetPinInterruptConfig(BOARD_INITPINS_NEW_IO_PORT, BOARD_INITPINS_NEW_IO_PIN, kPORT_InterruptFallingEdge);

    /* PORTC1 (pin 37) is configured as PTC1 */
    PORT_SetPinMux(PORTC, 1U, kPORT_MuxAsGpio);

    /* PORTC6 (pin 42) is configured as UART0_RX */
    PORT_SetPinMux(BOARD_INITPINS_DEBUG_UART_RX_PORT, BOARD_INITPINS_DEBUG_UART_RX_PIN, kPORT_MuxAlt4);

    /* PORTC7 (pin 43) is configured as UART0_TX */
    PORT_SetPinMux(BOARD_INITPINS_DEBUG_UART_TX_PORT, BOARD_INITPINS_DEBUG_UART_TX_PIN, kPORT_MuxAlt4);

    SIM->SOPT5 = ((SIM->SOPT5 &
                   /* Mask bits to zero which are setting */
                   (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))

                  /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
                  | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)

                  /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
                  | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
}

 

It throws an exception on this line:

 

    /* PORTA0 (pin 1) is configured as PTA0 */
    PORT_SetPinConfig(BOARD_INITPINS_NEW_IO_PORT, BOARD_INITPINS_NEW_IO_PIN, &NEW_IO);

 

So, where have I gone wrong with the FRDM-KW41Z board?

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