I have a question about SRAM interface.
There is a register 188.8.131.52 Module Control Register (MCR).
There is a description WPOL0 WAIT/RDY# polarity for NOR/PSRAM, but there is no WAIT/READY pin in table 24.4.3 Pin Mux in SEMC.
Is it possible to use WAIT/READY for SRAM? if possible, which pin is assigned to WAIT/READY?