Tl;DR: The LPSPI ISR is executed three times instead of two times as expected. Normally the first and third ISR calls are expected and the second ISR is unexpected. The unexpected ISR occurs when the LPSPI module is apparently "busy". Sometimes with large number of interrupts, the unexpected LPSPI ISR occurs after the two expected ISRs and it keeps interrupting the CPU until the module is re-initialized.
The software tools we use are:
S32 Design Studio v1.3
S32K144 SDK RTM 1.0.0
GHS Compiler for ARM
The hardware is a custom application specific board with a 64-pin S32K144 (057U maskset).
We use LPSPI0 module to communicate with an ASIC at 1Mbps. The MCU is the master and the ASIC is the slave.
Normally, 8bits of data (read command + register address) is sent to the ASIC from the MCU and the ASIC responds with 32 bits of data, all within once chip select low period. This data is then stored in RAM using the DMA. This is repeated every 500us.
After 10 such reads, the DMA ISR is executed where the LPSPI module is configured for 16-bit interrupt-based communication instead of DMA-based communication. 16bits of data is then written to the LPSPI buffer and transmission is started. Once transfer of 16-bits is complete, the LPSPI module calls the ISR (1st expected ISR) in which the LPSPI driver calls a callback function. In the callback, the received data is read (and discarded) and another 16-bits of data is filled in the buffer for transmission. After this second 16-bits are transferred, in the callback from LPSPI driver (2nd expected ISR), the LPSPI module is again configured for DMA-based transfer and the process repeats.
Under normal circumstances, we noticed that the LPSPI ISR is being executed thrice, two of which is expected as described above and one execution is unexpected. During the unexpected ISR execution only MBF in Status Register of LPSPI0 is set. There are 2 words in the TX Buffer as expected and no error flags are set.
A visualization of the interrupt execution times is in the below image.
A port pin was made high when the ISR execution began and made low before returning from the ISR.
The upper section of the image shows the three ISR executions while the lower section of the image is zoomed into the first two ISRs.
Gap between the first and second ISR is 1us.
We originally found the issue when testing the system under high CAN interrupt load.
We found that if there are a large number of CAN interrupts, sometimes this unexpected LPSPI interrupt occurs after the second expected LPSPI interrupt. But for some unknown reason the LPSPI module keeps interrupting the CPU from then onwards until the module is reconfigured. This is visualized in the image below.
The yellow signal on top is a port pin toggled every 10ms.
The blue signal in the middle is the execution of the LPSPI0 ISR.
The pink signal is the Chip select line of LPSPI0.