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NXP LS1012a FRDM - GIC Virtualization

Question asked by David Loosli on Mar 21, 2019
Latest reply on Mar 25, 2019 by David Loosli

Hi everyone



I am still trying to port an OpenSource hypervisor (i.e. Muen SK) to the ARMv8-A AArch64 architecture and decided to use the NXP LS1012a FRDM evaluation board as the target platform. The Kernel is written in Ada/SPARK.


Everything went well so far and I am now working on the implementation of the generic interrupt controller (GIC). While the physical interrupts are working perfectly, I have some problems with the maintenance interrupts for the virtual CPU interface (official ARM PPI Interrupt ID 25). As soon as a maintenance interrupt occures, the code execution switches correctly from the VM code at Exception Level 1 to the hypervisor code at EL2. When I acknowledge the maintenance interrupt, it also changes its state correctly from pending to active. But it somehow reasserts immediately again to the state "pending and active". I then tried to clear the pending state by writing to the according ICPENDING register bit of the distributor, but still no success. I now found in the QorlQ LS1012A Reference Manual, chapter 5.2 (interrupt assignment), an interrupt entry "Virtual CPU interface maintenance interrupt core 0" with ID 229 - but this one does never switch to pending state.


So my questions - what is this SPI ID 229 interrupt for? And how do I have to use it for maintenance interrupt handling? Or can I manually "deassert" the official maintenance interrupt with ID 25?


I would appreciate your advices!



Thanks, David