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HRESET_B and RESET_REQ_B expectations in error conditions

Question asked by Scott Gerhold on Mar 19, 2019
Latest reply on Mar 19, 2019 by ufedor

When the T2080 is configured to read the RCW from SPI and there are errors determined in the SPI (bad address, bad CRC etc.) what are the expected states for these signals.


For example if the RCW itself is corrupted (some possible errors (not a complete list): a) corrupt preamble, b) illegal address, c) CRC error). Will the HRESET_B signal stay low when RESET_REQ_B is asserted low? Or will HRESET_B transition high. In the Ref Manual, it states in step 12 of section 4.6.1 that it waits for the PBL RCW to be completed (loading of all 512 bits). If the PBL reports an error during its process of loading the RCW data, the device reset sequence is halted indefinitely, waiting for another PORESET_B or hard reset. If HRESET_B isn't deasserted it seems impossible to cause a hard reset (you can assert PORESET_B at this point). It isn't until step 14 that HRESET_B goes high. There is not specific mention that RESET_REQ_B gets asserted, but I am assuming that is part of the error response.


Now what if the RCW passes (with a CRC placed directly after the RCW) but an error occurs in the PBL PBI commands that follow the RCW phase. I am assuming in this case that HRESET_B signal transitioned high after the RCW is loaded, before PBL PBI command loading is complete? So in this case it should definitely be HRESET_B = 1, RESET_REQ_B = 0?


It seems that ASLEEP is also usable to help decode states in this phase. However it appears that ASLEEP will be asserted (high) until both RCW and PBL PBI phases are complete (step 18 - System ready state). Thus it is possible that we could use ASLEEP to help determine when RESET_REQ_B assertions are the result of RCW/PBL or something after that phase. We are looking for ways in which we can signal to a technician that a boot up error is the result of the SPI PROM contents instead of something with the power supplies or boot SW.


What I am looking for is a definitive set of waveforms (or state diagram) that defines when the HRESET_B, RESET_REQ_B and ASLEEP signals would transition as it relates to the RCW/PBL phases.