In p.6 of the data sheet for PCAL6524 has the following description of additional quiescent supply current.
ADDR, SCL, SDA, RESET; one input at VDD(I2C-bus) - 0.6 V, other inputs at VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V
P port; one input at VDD(P) - 0.6 V, other inputs at VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V
It is a very high current as a quiescent supply current, but does it mean that a large quiescent supply current will flow if one port is 0.6 V lower than VDD?
The above-mentioned quiescent supply current does not occur if input voltage is within VDD-0.6V?