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S32K144 PDB ADC DMA

Question asked by weiqiang liu on Mar 16, 2019
Latest reply on Mar 17, 2019 by Petr Stancik

My current problem is: I can use the two channels of PDB1 (CH0\CH1) for triggering, CH0 can trigger for 8 ADC channels, but CH1 channel only triggers one channel. Please help analyze, thank you!
Application scenario: Based on our circuit design. At present, we use 12 channels of ADC1 (the ADC model we selected has only 12 channels).
For the understanding of this part of the manual:
1. BACK TO BACK mode is supported on all channels. As shown below

2. There are two BACK TO BACK modes, and the mode selection is selected by SIM_CHIPCTL[PDB_BB_SEL].
   2.1 When the first SIM_CHIPCTL[PDB_BB_SEL]=0. There is no direct connection between PDB0 and PDB1 (PDB0CH0, PDB1CH0), that is, the 8 pre-trigger channels of CH0 of PDB0 form a loop in sequence, and the 8 pre-trigger channels of CH0 of PDB1 form a loop to trigger in sequence.

 

2.2 When the second SIM_CHIPCTL[PDB_BB_SEL]=1. PDB0 and PDB1 form a large loopback (PDB0CH0-PDB1CH0), that is, the CH0 pre-trigger of PDB1 is completed after 8 pre-triggers of CH0 of PDB0 are completed.

3. Application analysis
Combined with our application field shadow (only 12 channels of ADC1 are used), we only use PDB1, as shown below

Combine the picture below,

So, we SIM_CHIPCTL[PDB_BB_SEL]=0, the first method in Section 2, to fulfill our requirements (this method applies to the S32K144 demand sent yesterday). 
In my program, I set the delay trigger value of the channel (guarante the value of the CH1 channel of PDB1 is later than the trigger time of the CH0 channel of PDB1) to realize the two channels triggering the two PDB1 in the counting period of one PDB. Channels (CH0\CH1).

 

During the debugging process, the trigger of the ninth channel is realized, as shown in the figure below.

Where RI is triggered by the CH1 channel of PDB1.

The current problem is that, according to the above analysis, if the PDB1 CH1 count can trigger the RI channel, it should be able to simultaneously trigger the 8-channel pre-trigger channel corresponding to CH1 (because PDB1 CH0 triggers 8 ADC channels at the same time), but Now only RI has implemented sampling.
I have read the PDB chapter of the reference manual in detail today. The conclusion is that when the PDB COUNTER counts, it is repeatedly compared with the delay setting value PDBCHnDLYm. When it is equal to this value, the corresponding pre-trigger channel corresponding to PDB1 CH1 is triggered to sample the ADC channel. If the corresponding delay setting value PDBCHnDLYm is reached, the bit corresponding to CF will be set. I intercepted the state of the relevant register of PDB1 during operation. The CF bit of CH0 of PDB1 is all ones, but the CF bit of CH1 channel of PDB1 is not all ones. There was no problem with the difference before the end.

 

Above, trouble to help analyze the problem, thank you!

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