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What is the timing associated with the IFC Transceiver Enable pin?

Question asked by Scott Gerhold on Mar 12, 2019
Latest reply on Mar 13, 2019 by ufedor

The QorIQ processor provide a Transceiver Enable pin to support fast/slow memories on the bus. But I cannot find anything in the documentation that details the timings for that signal - such as when does it actually get enabled during a transaction. Is it asserted as soon as ALE is asserted with the address for the transaction? When does it deassert - this is needed for controlling bus turn-around time. In particular I am interested in the T2080's implementation.

 

Please let me know where to look for this information.

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