Both i.MX6QP and i.MX6Q SABRE-SD board with Linux BSP L4.9.88.
It will be output MMC_CLK over 50MHz.
1) While Kernel booting, MMC_CLK will be output 200MHz clock from MMC_CLK.
2) After Kernel booting,
2-1) After the 50MHz MMC_CLK output has stopped for a short time, the 100 MHz clock is output twice.
2-2) After leaving for a while, a 50 MHz clock is output and it transitions to a 100 MHz clock.
What is root causes of this problem?
In this time, eMMC used as both boot and system root file device.
Is it OK to output over 50MHz clock from MMC_CLK?
To see waveform, MMC_CMD and MMC_DATA0 are keeping Hi Level, so it have no problem to
boot and read/write from eMMC.
I attached waveform files for all operation.
Signal name of each ch as following.
CH1 : MMC_CLK
CH2 : MMC_CMD
CH3 : MMC_D0