i.MX6QP output over 50MHz from MMC_CLK

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

i.MX6QP output over 50MHz from MMC_CLK

1,065 Views
takayuki_ishii
Contributor IV

Hello community,

Both i.MX6QP and i.MX6Q SABRE-SD board with Linux BSP L4.9.88.

It will be output MMC_CLK over 50MHz.

1) While Kernel booting, MMC_CLK will be output 200MHz clock from MMC_CLK.

2) After Kernel booting,

2-1) After the 50MHz MMC_CLK output has stopped for a short time, the 100 MHz clock is output twice.

2-2) After leaving for a while, a 50 MHz clock is output and it transitions to a 100 MHz clock.

What is root causes of this problem?

In this time, eMMC used as both boot and system root file device.

Is it OK to output over 50MHz clock from MMC_CLK?

To see waveform, MMC_CMD and MMC_DATA0 are keeping Hi Level, so it have no problem to

boot and read/write from eMMC.

I attached waveform files for all operation.

Signal name of each ch as following.

CH1 : MMC_CLK

CH2 : MMC_CMD

CH3 : MMC_D0

Best regards,

Ishii.

Labels (3)
0 Kudos
5 Replies

893 Views
takayuki_ishii
Contributor IV

Hello Artur,

Thank you for your reply.

I found a reason of the 2-1) problem. It is generated to assert SOFTWARE_RESET (uSDHCx_SYS_CTRL[RSTA]=1) in

function esdhc_writeb_le() of root/drivers/mmc/host/sdhci-esdhc-imx.c.

MMC driver will be generate it asynchronously.

Does it need to stop MMC_CLK output before set Software Reset for ALL bit by uSDHCx_VEND_SPEC[FRC_SDCLK_ON] = 0?

Best regards,

Ishii.

0 Kudos

893 Views
art
NXP Employee
NXP Employee

Q. Does it need to stop MMC_CLK output before set Software Reset for ALL bit by uSDHCx_VEND_SPEC[FRC_SDCLK_ON] = 0?

A. To forcedly disable the card clock, you have to uSDHCx_VEND_SPEC[CARD_CLK_SOFT_EN] = 0. Better is to do it before resetting uSDHC.

Best Regards,

Artur

0 Kudos

893 Views
art
NXP Employee
NXP Employee

On both i.MX6Q and i.MX6QP SABRE SD boards, eMMC chips are 4.41 spec compatible, so, the maximum operational clock frequency for them is 52MHz. However, according to your observations, when eMMC is in non-operational state, the clock occasionally switches to a higher frequencies for some reason. This may be classified as a minor bug of the L4.9.88 BSP release. However, since the higher clock frequency is only applied when eMMC is in non-operational state, it should not affect the regular system operation.


Have a great day,
Artur

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

0 Kudos

893 Views
takayuki_ishii
Contributor IV

Hello Artur,

Thank you for your response.

You say that it is a minor bug and not affect the regular system operation.

But this problem seems not only L4.9.88BSP but also other BSP's like a Linux BSP L4.9.11 and Android N7.1.2.

And continuing to apply a high frequency clock can adversely affect the circuit.

Is it really OK even if it possible be in non-operation state?

By the way,  To apply following patch, it seems that it is effect to fix the problems of 1) and 2-2).

[v2,1/2] mmc: sdhci-esdhc-imx: disable clocks before changing frequency - Patchwork 

But 2-1) can not fixed yet.

Best regards,

Ishii.

0 Kudos

893 Views
art
NXP Employee
NXP Employee

When in non-operational state, the issue does not affect the circuit.

Artur

0 Kudos