Please explain to me what was meant and whether there is an error here:
page 15, table 13, STEP_TIME_GRP0 to STEP_TIME_GRP3, step time control registers
It follows from the table that for the STEP_TIME_GRP0 register, the seventh bit is reserved (!) And thus we cannot control the step time (rise / fall) for a group of zero?
Perhaps this is a document layout error?
Maybe there should be such a distribution of bits for the registers indicated in Table 13:
0x29 STEP_TIME_GRP0 bit 7
0x2d STEP_TIME_GRP1 bit 7
0x31 STEP_TIME_GRP2 bit 6
0x35 STEP_TIME_GRP3 bit 6
How really should be?