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There meet a question about HCS12 Chip's SCISR1Register

Question asked by 崇锐 卢 on Mar 8, 2019
Latest reply on Mar 8, 2019 by Diana Batrlova

When I debug my uart process,I found my uart process  runs unusual.

Then I found the SCISR1's OR bit can not be clear and set with out RDRF bit set.

Usual when RDRF bit and OR bit set at the same time I can clear them all by read scisr1 regiser and scidrl

But I check datasheet I can't find the discrib about this abnormal situation.