I'm trying to implement PLL1 to set the main clock frequency for the M4 core at most 204MHz.
To set the PLL1 with the PLL1_CTRL register there are no problems. I perform the following instructions:
1) Set AUTOBLOCK
2) Set M and N
3) wait LOCK
4) Set DIRECT
5) wait LOCK
6) clear BYPASS
7) wait LOCK
Each setting is set and the LOCK in PLL1_STAT is always 0.
Unfortunately, when I finally select the CLK_SEL of BASE_M4_CLK at 0x9, the next instruction is no longer executed.
Even if I do this last setting before setting up the PLL1, it does the same problem.
What could be the reason?